Kodsnack 411 - The performance to generate the next CPU, with Wilson Snyder

Kodsnack in English

Fredrik chats with Wilson Snyder about Verilator, chip design, performance, and open hardware.

This episode is a bit of a follow-up to episode 389 where Robert Wikander talked - in Swedish - about verification of circuit designs. Afterward, Robert mentioned that we should really ask Wilson Snyder to talk about Verilator, and here we are! Wilson works with CPU and other hardware design, and is one of the lead developers of Verilator. When you design hardware, hardware description languages come in handy - you use them to describe hardware precisely. Then you can generate runnable code simulating the hardware, and run batteries of tests against it without needing to manufacture physical hardware.

Verilator is one tool for turning code in the Verilog hardware description language into C++ or Systemc. The major competing tools are more on the interpreter side - which means that Verilator usually has a performance advantage. Oh, and it’s GPL licensed as well. As we discuss, Verilator doesn’t actually support all of Verilog, but that’s being worked on. And increased performance in itself is a clear goal of both research and concrete improvements.

We also discuss a bit what might come out hardware-wise in the future. Wilson predicts DPUs - data-offload units, basically - will become even more of a thing than today.

The second part of the discussion is focused on Verilator itself - how it’s built, designed, and developed. People with knowledge of compilers will feel right at home inside the Verilator source code.

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Links

• Wilson Snyder
• Robert Wikander - appeared in episode 389 (in Swedish)
• Digital equipment
• Verilator
• Hardware verification
• Synthesis - converting the language used into hardware gates
• Emacs
• Linus - yes, Torvalds
• GPL 2
• GPL 3
• Compiler
• Interpreter
• CHIPS alliance
• Duane Galbi got Verilator open sourced
• Tarball
• Systemc
• EDA - Electronic design automation
• Cadence
• Synopsys - provides synthesis tools
• Git
• RISC-V
• Open cores
• FPGA
• Open source ARM and MIPS cores
• Standard cell
• DSP
• Amiga
• ML
• GPUs
• DPUs
• Parsing
• Lexing
• Verilator on Github
• Verilator’s Github issues
• UVM - Universal verification methodology
• veripool.org

Titles

• An open source tool that could do verification
• It started as a hobby
• It has a life of its own
• Into actual hardware gates
• Matching the languages
• A good escape story
• It’s bascially a compiler
• Open source hardware design
• The performance to generate the next CPU
• Innovation feedback cycles
• Download a core
• Always a little bit of a focus
• My real job is CPU design